这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用...

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实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)

SPI接口协议，将spi总线转换成为LOCALBUS总线(SPI interface protocol, the spi bus converted into LOCAL BUS bus)

基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。

UMC 90nm design kit. please read before using thee models.

使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言(Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language)

利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。(Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.)

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

很多VHDL例子，没有测试，供大家参考-VHDL many examples, there is no test, for your reference

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。