这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用...

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)

系统数字逻辑电路设计方法以及示例的介绍,分析较好,有价值(System digital logic circuit design methods and introduce examples, analyze good and valuable)

detection of the following sequence ‘10110110’in VHDL

Multiplexer styles in VHDL

沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)

FPGA UART transmit and so on

温度液晶显示演示程序 LCD数据线：P0口 LCD控制线：RS P20 RW P21 E P22 BUSY P07 18B20端口DQ ：P27 (Temperature of liquid crystal display demo Data line: P0 LCD LCD RS P20 RW P21 control line: E P22 BUSY P07 18B20 DQ : P27 port )

DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)

其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)