步进电机控制程序，用vhdl实现。可实现电机的正反转控制

实现温度显示，接温度传感器。在4数码管上显示小数点后两位的温度(temperture of FPGA)

一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,

数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.

自适应均衡器

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

i2c master ip for altera nios, add in qsys

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials

在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)

说明：  使用FPGA实现RGB图像转灰度图像的算法，下载入自己的电路板可直接将摄像头拍摄到的图像实时转换成灰度图像(FPGA is used to realize the algorithm of transforming RGB image into gray image. The image captured by the camera can be converted into gray image in real time by downloading it into its own circuit board)