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Multiplier
圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)
- 2012-10-25 21:12:49下载
- 积分:1
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juchibo
用vhdl语言生成锯齿波,数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)
- 2011-12-21 19:29:51下载
- 积分:1
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interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分:1
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基于无源蜂鸣器和矩阵按键的电子琴系统设计
基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1
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The use of FPGA to collect the new U.S. accelerometer data and the data collecte...
利用FPGA来采集美新加速度计的数据,并将FPGA采集到的数据传给ARM系统处理-The use of FPGA to collect the new U.S. accelerometer data and the data collected FPGA passed ARM system processing
- 2022-02-04 12:49:36下载
- 积分:1
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Adder4
本设计是设计了一个4位全加器的内容,是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)
- 2009-05-11 19:50:58下载
- 积分:1
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VGA-VHDL-Design
本文件给出了基于VHDL语言的VGA图像显示程序及其工程问件。(This document is presented based on VHDL language VGA image display program and the project asked the pieces.)
- 2010-06-19 11:35:12下载
- 积分:1
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AX301
黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)
- 2021-03-23 21:59:15下载
- 积分:1
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TDMsystem
实现多路可变时分复用,包括复接器,解复接,比特同步,帧同步,分频器(Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider)
- 2018-09-16 23:29:09下载
- 积分:1
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verilog编写的流水线模块
verilog编写的流水线模块-Verilog modules prepared by the Pipeline
- 2022-03-30 09:04:46下载
- 积分:1