本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))

给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)

ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)

基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

vhdl语言编程入门实例100个，部分附有仿真波形图，和一些基本的讲解-vhdl examples

说明：  NAND FLASH的多个仿真模型，可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)