本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...

频率计，测量频率。可测范围为100HZ至60khz.测量比较稳定。基于MSPg2553(Frequency meter, measuring frequency. Measurable range 100HZ to 60khz. Stable measurement)

FPGA设计流程指南 介绍基本的设计方法-FPGA Design Process Manual

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)

cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)