本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...

重点介绍了双线性插值算法和该方法的Ｆ Ｐ ＧＡ硬件实现 方法， 包括图像数据缓冲单元、 插值系数生成单元以及插值计算单元等。(Highlights the bilinear interpolation algorithm and the method of F P GA hardware The method includes an image data buffer unit, the interpolation coefficient generating unit and an interpolation computing unit and the like.)

《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)

维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA(viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA)

Mini AES Advanced Encryption Standard (AES) implementation with small area/resources utilization. Features - Encryption and Decryption unit in single core.

网上分享的一段100例子，适合FPGA学习的初学者。内部还有一些经典实用技巧。                                                                        

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)

说明：  IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)

说明：  qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

vhdl code for 8051 processor