ADS8325caiyang konfgzhi

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

说明：  verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)

基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)

FSM_test for textbanch in vhdl-FSM_test

FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合-FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

EDA应用中RAM具体定义实例，供大家学习和写程序参考之用-EDA applications, examples of the specific definition of RAM, for everyone to learn and write programs for reference

矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码(Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench)