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ALU_74181_me
学习ALU的设计方法。
2、用HDL语言采用行为描述的方法完成74181的逻辑设计 。(Learn the design method of ALU.
2, use HDL language to use behavioral description method to complete 74181 logical design.)
- 2020-11-11 16:19:44下载
- 积分:1
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Escalimetro
all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display
- 2012-12-25 02:14:17下载
- 积分:1
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VC707_MIG_DDR3
说明: VC707_MIG_DDR3.sim文件夹中是仿真的文件:testbench和DDR3模型参数
VC707_MIG_DDR3.srcs文件夹中是源文件,包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters
VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)
- 2020-10-16 19:20:53下载
- 积分:1
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tlc5615
TLC5615串行DA的驱动接口,采用verilog编程(TLC5615 driver DA serial interface using verilog programming)
- 2009-04-27 11:59:22下载
- 积分:1
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1024
1024点FFT快速傅立叶变换,(vhdl代码)-1024-point FFT vhdl
- 2022-04-25 16:04:00下载
- 积分:1
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FPGA-DSP
vhdl编写的FPGA与DSP接口程序,在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)
- 2021-01-08 10:58:51下载
- 积分:1
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奇数奇偶校验器使用VHDL的有限状态机
An odd parity checker as an FSM using VHDL
- 2022-02-24 23:42:29下载
- 积分:1
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it performs the serail dividing operations
it performs the serail dividing operations
- 2022-11-07 21:55:03下载
- 积分:1
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rscode
RS编码器在fpga上的实现,用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)
- 2009-06-11 21:45:49下载
- 积分:1
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并串转换
利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。
- 2023-06-03 10:20:03下载
- 积分:1