并串转换

在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

HDLC控制器源码，包括单独HDLC的Tx端和Rx端实现，以及顶层带FIFO和Wishbone总线控制器的实现，通过Wishbone可方便与CPU连接，通过软件控制整个HDLC控制器的工作。

采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)

用FPGA产生正弦波、方波、三角波和锯齿波，可以通过按键控制输出波形及其频率，并且可以通过lcd显示输出的波形名字及频率

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )

XAPP928,可以参考学习.里面包含了色温调整、GAMMA调整以及空间抖动增强灰度算法，这３个基本是现在平板显示设备常用的图像预处理算法。

LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)

an example HDL-Core with any basic gates.