奇数奇偶校验器使用VHDL的有限状态机

verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support

辛辛苦苦的作品应用于DE2 的 开发。。希望对大家有用。-hard work for Dictyophora development. . We hope that the right useful.

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)

LDPC码的短循环对LDPC码性能的影响 (Short Protograph-Based LDPC Codes)

在接收信号的数字化、软化的实现中,数字下变频起着重要的作用。本文首先介绍了数字下 变频的组成结构,然后详细分析了数字下变频的工作原理,描述了在实现数字下变频时,设计方案所 采用的高效滤波器———CIC 滤波器和多相抽取滤波器的结构和原理。最后,用通过Simulink 对数字 下变频的性能进行了仿真。在仿真的基础上使用Insight 公司的FPGA 开发系统,用测试电路实测了 数字下变频的性(In the receiving digital signal, softening the realization, the digital down-conversion plays an important role. This article first introduced the digital down conversion of the composition, and then a detailed analysis of digital down conversion of the working principle described in the realization of digital down conversion, the design used in high-performance filters--- CIC filters and multi-phase extraction filter structure and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of)

一个在CPLD，EPM70128上实现的PWM控制源程序。(A CPLD, EPM70128 realize the PWM control on the source.)

Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)

在altera DE2 的开发板上采集图像，到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.

D触发器的基本功能的理解及应用，特别是记忆传输功能使用WAIT语句编写地理解-D flip-flop understanding of the basic functions and applications, in particular the memory transfer function using the WAIT statement is prepared to understand