奇数奇偶校验器使用VHDL的有限状态机

FPGA上使用硬件描述语言实现俄罗斯方块游戏，该游戏支持PS2键盘输入，VGA视频输出，游戏可以选择不同的难度，同时可以记录显示游戏得分，同时包含VC上位机方块形状编辑器的一整套项目方案

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

Learning Verilog Chinese Version Part 8

用于压缩感知 OMP 算法非常适合于压缩感知

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！(Verilog FPGA internal 8051 core, super, super hard to find! Shared out!)

具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)