奇数奇偶校验器使用VHDL的有限状态机

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

Implementation of CORDIC atan block in VHDL

vhdl的基础性的介绍，对初学者大有用处-vhdl basic introduction

资源描述该乘法器可用于过滤器，算术运算和；

简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

bios spi flash acer 5740g

Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear