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decoder_38
这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)
- 2013-08-04 09:53:07下载
- 积分:1
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Farrow-filter-design
两篇中文论文,详细叙述了Farrow滤波器的设计方式和理论基础,非常实用!(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)
- 2013-11-15 17:15:20下载
- 积分:1
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用FPGA实现的VGA接口程序,采用的语言是VHDL硬件描述语言,大家可以参照下看看采用的器件是Altera EP2c35...
用FPGA实现的VGA接口程序,采用的语言是VHDL硬件描述语言,大家可以参照下看看采用的器件是Altera EP2c35-Using FPGA to achieve the VGA interface program, the language used is VHDL hardware description language, we can see under the light of the devices used are Altera EP2c35
- 2023-09-07 02:45:04下载
- 积分:1
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a2013_TCAS_NB-LDPC_decoder
Design of a GF(64)-LDPC Decoder Based on the
EMS Algorithm
- 2016-06-17 18:04:14下载
- 积分:1
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用VERILOG HDL实现的任意 频率分频器源代码,是一个通用的程序...
用VERILOG HDL实现的任意 频率分频器源代码,是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
- 2022-03-25 15:26:54下载
- 积分:1
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uart
UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)
- 2011-08-25 09:32:35下载
- 积分:1
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用vhdl实现24小时计数器,方法简单实用。 仿真环境MAXPLUS
用vhdl实现24小时计数器,方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
- 2022-03-24 12:46:20下载
- 积分:1
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grlib-gpl-1.1.0-b4108
gaisler公司在2011年发布的的leon3的源代码!(source code of leon3 )
- 2012-05-12 00:12:20下载
- 积分:1
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FPGA_can
实现基于FPGA的控制MCP2515发送的程序,本人编写通过测试,希望提供帮助(FPGA-based control program sent MCP2515, I write to pass the test, hoping to help)
- 2020-12-31 09:28:59下载
- 积分:1
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cloc
时钟在单片机中的应用,用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)
- 2013-06-04 15:27:35下载
- 积分:1