奇数奇偶校验器使用VHDL的有限状态机

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

1 前大灯可以随意打开和关闭； 2 当汽车左转弯的时候，前左转向灯闪烁，同时左后灯的3盏灯由右往左闪烁； 3 当汽车有转弯的时候，前右转向灯闪烁，同时右后灯的3盏灯有左往右闪烁； 4 当汽车减速或紧急刹车的时候，左后灯和右后等同时闪烁； 5 当汽车在左转弯的同时减速，则前左转向灯闪烁，左后灯的3盏灯由右往左闪烁，同时右后灯都点亮。 6 当汽车在左转弯的同时减速，则前右转向灯闪烁，右后灯的3盏灯有左往右闪烁，同时左后灯都点亮。 -a former headlamps can be opened and closed at will; 2 when the vehicle made a left turn when the former left to lights flickered. Left lights while the three lights flashing from right-go left; 3 when the vehicle is making a turn when a right turn to the former lights flickered. Right after the lights while the three lights are blinking right and left; 4 when the vehicle deceleration or when the emergency brake, Left and right after the lights blink, and so on; 5 when the vehicle made a left turn at the same time to slow down, and then to the left before the lights flickered. Left lights three lights flashing from right-go left, right after the lights are lit. 6 when a car made a left turn at the same time to slow down, and then right before the lights to flick

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages

很好的fft学习程序感兴趣的同学可以看哈，下载一下。(it is very good )

中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)

说明：  VHDL语言写的SRAM控制程序，在开发板上验证过。(Written in VHDL SRAM control procedures, the development board verified.)

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

说明：  perl学习资料，包含一些常用的一些文档，可直接做来用于实践(perl training)