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4BITMUIT
利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
- 2013-09-05 10:06:52下载
- 积分:1
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m_xulie
在quaritusII的开发环境下,verilog语言编写的m序列发生器代码,这种算法简短而有效,非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)
- 2013-09-26 11:30:47下载
- 积分:1
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vhdl-cordic-atan-master
Implementation of CORDIC atan block in VHDL
- 2019-05-14 16:51:26下载
- 积分:1
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vhdl的基础性的介绍,对初学者大有用处
vhdl的基础性的介绍,对初学者大有用处-vhdl basic introduction
- 2022-05-20 01:22:09下载
- 积分:1
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8位乘法器的VHDL代码
资源描述该乘法器可用于过滤器,算术运算和;
- 2022-08-14 19:11:01下载
- 积分:1
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CPU-Verilog
简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分:1
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shuzijishiqi
基于VHDL的数字计时器,手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))
- 2016-12-05 19:57:07下载
- 积分:1
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quartusii 三分频电路,大家帮参考一下,有什么问题
quartusii 三分频电路,大家帮参考一下,有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem
- 2022-03-17 05:41:25下载
- 积分:1
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JV50128
bios spi flash acer 5740g
- 2013-06-28 18:48:06下载
- 积分:1
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Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核...
Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
- 2022-02-06 18:05:18下载
- 积分:1