收集的QuartusII的使用手册，包含了几个pdf文件，比较不错的参考手册...

quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容

基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

qspi接口控制，指令包括spi、dual spi、quad spi，通过验证，供参考(Qspi interface control, including spi, dual spi, quad spi, for reference.)

一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.

r80515源代码，包含说明文档。FPGA验证通过(r80515 source code, including documentation. Verified by FPGA)

采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)