-
bt656_decode
说明: 将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分:1
-
fpga超声波测距
FPGA开发超声波测距,可改写工业探伤或倒车测距等系统,quartus2下选择EP2C5Q208C8(CycloneⅡ) 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 !!注意:移植程序仅需重新约束数码管和超声波模块的针脚
(Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)
- 2022-07-17 19:43:35下载
- 积分:1
-
decode_64_66
自编的64B/66B解码程序,做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)
- 2020-10-16 10:07:29下载
- 积分:1
-
openmips
一个开源mips处理器verilog 源码(wishbone interface wishbone interface)
- 2020-08-16 15:48:32下载
- 积分:1
-
ofdm的verilog程序
利用FPGA实现
ofdm的verilog程序
利用FPGA实现-OFDM FPGA using the Verilog procedures realize
- 2022-08-07 01:11:15下载
- 积分:1
-
random
Verilog使用$random()函數簡單範例(Verilog using the $ random () function of a simple example)
- 2009-06-18 11:54:19下载
- 积分:1
-
这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分:1
-
aulap3_IsadoraStangarlin
Code developed in classroom
- 2017-09-28 00:51:06下载
- 积分:1
-
用Actel公司的Fusion系列FPGA开发的RTC实验程序
用Actel公司的Fusion系列FPGA开发的RTC实验程序-With Actel" s Fusion Series FPGA development of experimental procedures RTC
- 2023-05-31 08:10:02下载
- 积分:1
-
这个RAR文件包含有关FPGA和CPLD的呈现。
This rar files contains the presentation about FPGA and CPLD .
- 2022-07-13 06:31:38下载
- 积分:1