VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.

isa MEMORY PLAN eu biu asm

fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

ethernet 10 0M MAC-ethernet MAC 10,100 M

vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl　adder vhdl　adder vhdl　adder

说明：  基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)

用fpga驱动lcd的原代码，是用vhdl语言实现的-drive lcd by fpga，the source program is written by vhdl

此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.

一款介绍Soc使用的PDF文档供大家看和实践，还是有一定参考价值的！-A description Soc using PDF documents for everyone to see and practice, there are still some reference value!

Verilog实现的VGA程序，用ISE打开工程文件即可-Verilog implementation VGA program, open the project file with the ISE can be