8. For the key to enter a password lock, assuming that reset after the seven lam...

用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)

FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)

自己编写的C++的类的测试程序，有详细的注注释，对初学者有很大帮助！！！(The own written C++ class test program, detailed annotation of Note of great help for beginners! ! !)

自适应滤波，对输入信号进行选择性的加权处理，使输出达到最优化，并且能够跟踪和适应系统和环境的动态变化(Least mean square，of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)

protel中fpga封装库3，非常难找的-protel library in fpga package three, very difficult to find the

基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)

endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)

8bit/10bit编码Verilog实现(8bit/10bit Verilog Code)