流水线乘法器的VHDL实现，希望对你会有用！

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

ModelSim的使用如何操作和使用以及安装如何安装

代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt (Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)

altera remote updata cyclone5 平台例程，无nios核版本(altera remote updata cyclone5 platform routine do not use nios)

FPGA开发仿真工具modelsim的高级进阶教程，包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)

利用verilog实现对SD卡的控制，可以实现对SD卡的读写。(Verilog SD)

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

0-99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦 -0-99 notation VHDL source, comprehensive guide book on the experiment can be used by everyone to download Oh

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)

用FPGA产生正弦波、方波、三角波和锯齿波，可以通过按键控制输出波形及其频率，并且可以通过lcd显示输出的波形名字及频率