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verilog
用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)
- 2021-04-25 20:48:46下载
- 积分:1
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系统介绍EDA技术的发展概述,相关概念,VHDL语言、MAX+PULS、QUARTUS的设计方法。...
系统介绍EDA技术的发展概述,相关概念,VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.
- 2022-07-09 22:03:23下载
- 积分:1
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VHDL的食谱
The VHDL Cookbook
First Edition
July, 1990
Peter J. Ashenden
Dept. Computer Science
University of Adelaide
South Australia
- 2023-02-13 13:30:04下载
- 积分:1
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CORDIC算法的vhdl实现,包含一个说明文件
cordic算法的vhdl实现,内附有文档说明-cordic algorithm vhdl realized, a document containing a note
- 2022-01-26 06:23:45下载
- 积分:1
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costas
matlab科斯塔斯环的仿真,有波形,很实用的程序(matlab costas m programm)
- 2017-06-17 09:08:11下载
- 积分:1
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buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键...
buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press
- 2022-12-12 05:35:03下载
- 积分:1
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table-for-sin-functionof-
DDS中的正余弦生成,初始相位相差90度,可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)
- 2013-12-17 22:09:56下载
- 积分:1
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multiplexersemultiplexer
this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2009-12-21 18:11:27下载
- 积分:1
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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码,需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分:1
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QC_LDPC译码器的FPGA设计
说明: LDPC码的FPGA实现,用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)
- 2019-11-15 06:04:33下载
- 积分:1