verilog 入门概述 新手学习资料

MODELSIM的实验程序，在QUARTUSii中调用MODELSIM，实现仿真-ModelSim Experimental procedures QUARTUSii call MODELSIM, realize Simulation

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

说明：  4位加法器，4位数字相加及进位功能的实现，主要利用Verilog语言实现，简单轻松，且代码量少(a adder which can realize 4 bit numbers adding)

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)

un controller pi par le langage VHDL xilinx ise design 13.2

说明：  Simetrix EMI滤波器设计，实际测试有效果。(Simetrix EMI filter design, the actual test results are effective.)

格子玻尔兹曼方法模拟poiseuille流，半反弹边界，适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)

调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)

verilog code,about oc8051

INTEL 微处理器 第八版 答案 从第二章开始，奇数偶数的答案都有。(INTEL microprocessor eighth edition answer from the beginning of the second chapter, the answer has odd and even.)