采用VHDL编写的七段数码管显示程序

位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog

说明：  altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)

通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)

VHDL implementation using mouse and monitor

it shows bcd counter

6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable

主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)

FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System

实现qpsk解码，适合新手学习，代码简单，好用(mplementation of QPSK decoding)

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))