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系统设计
说明: 基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)
- 2020-06-21 02:20:01下载
- 积分:1
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Experiment_1_Xilinx
很不错的FPGA入门级实验指导书,按照实验的知道,能够学会使用ISE仿真简单的流水灯。教程较为详细,从硬件连接到代码编写都做了详细指导,适合新手入门。(Very good entry-level FPGA experimental guide books, according to the experiment know, be able to learn to use the ISE Simulator simple water lights. Tutorial in detail, the hardware connected to the coding have done a detailed guide for beginners.)
- 2016-09-16 23:07:26下载
- 积分:1
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本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材...
本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching
- 2022-01-26 04:23:45下载
- 积分:1
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介绍了光纤光栅感温火灾探测系统的应用原
理,并重点阐述了用CPLD 设计虚拟MC14499 器件模
块,给出并解释了用Verilog HDL 语言实现的...
介绍了光纤光栅感温火灾探测系统的应用原
理,并重点阐述了用CPLD 设计虚拟MC14499 器件模
块,给出并解释了用Verilog HDL 语言实现的部分程
序和仿真测试结果。-Introduction of Fiber Bragg Grating temperature fire detection system principles, and focuses on the use of CPLD design virtual MC14499 device module, are given and explained using the Verilog HDL language to achieve some of the procedures and simulation test results.
- 2022-03-01 16:23:41下载
- 积分:1
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18_vga_test
说明: 基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)
- 2019-04-01 13:47:46下载
- 积分:1
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RS_5_3_CODEC
完成RS(5,3)编码程序,运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)
- 2010-05-25 21:21:34下载
- 积分:1
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raylrnb (3)
说明: 本资源有一个matlab程序段,是仿真BPSK分别在高斯噪声和瑞利衰落下的误码率,产生图形对仿真值和理论值进行比较(This resource has a matlab program segment, which is the bit error rate of simulated BPSK under Gaussian noise and Rayleigh fading respectively. The generated graph compares the simulated value with the theoretical value.)
- 2019-10-21 21:16:04下载
- 积分:1
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DE2_115_TV
这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)
- 2013-03-06 21:49:22下载
- 积分:1
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XAPP_585
XAPP585 serdes_1_to_7 and serdes_7_to_1 data
- 2021-02-04 13:49:57下载
- 积分:1
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Block-cipher-lock
密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分:1