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FPGA-DSP
FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)
- 2017-05-31 10:36:17下载
- 积分:1
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单片机课程设计——交通灯_1
一个交通灯设计,简单的实现,没有添加其他的显示管(Traffic Light System)
- 2020-06-21 10:40:02下载
- 积分:1
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FPGA
基于FPGA实现移位乘法功能,已经验证,十分好用。-FPGA-based multiplication realize shift function, has been verified, is very easy to use.
- 2022-02-07 13:03:46下载
- 积分:1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码,能够实现时分秒的计时,可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分:1
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程序是用硬件描述语言(VHDL)实现:4×4键…
程序主要是用硬件描述语言(VHDL)实现:
4*4键盘扫描,简洁明了,通俗易懂,比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
- 2022-01-31 18:02:15下载
- 积分:1
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SCRAMBLER
32位扰码器的verilog代码,编译通过(The Verilog code of 32_bit scrambler)
- 2009-11-24 14:51:38下载
- 积分:1
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杰姆斯阿姆斯壮的VHDL设计,源代码
James Armstrong VHDL Design , source code
- 2022-09-04 01:55:03下载
- 积分:1
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DDSN
quartus II 13.0 DDS工程文件,采用VHDL编写,可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)
- 2021-03-20 16:49:17下载
- 积分:1
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VHDL
带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)
- 2020-06-30 03:00:02下载
- 积分:1
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VHDLFIFO
用Verilog 写一个8x16 的FIFO,完成先入先出的功能,并且在FIFO读空时输出EMPTY
有效信号,读指针RP 不再移动;FIFO 写满时输出FULL 有效信号,并且即使WR 有效也
不再向存储单元中写入数据(写指针WP 不再移动)。
(NO)
- 2020-09-20 20:17:51下载
- 积分:1