Digital signal source, the output of different frequency, phase is the cosine si...

这篇文章主要是概要的阐述了如何使用-quartusⅡ+Modelsim+synplify pro，来设计FPGA系统。-This is a summary of the main article on how to use the-quartus Ⅱ+ Modelsim+ synplify pro, to design FPGA systems.

一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners

D触发器的基本功能的理解及应用，特别是记忆传输功能使用WAIT语句编写地理解-D flip-flop understanding of the basic functions and applications, in particular the memory transfer function using the WAIT statement is prepared to understand

HDL编程风格，很有用,希望对大家有所帮助。-HDL programming style, very useful, we want to help.

dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.

下采样与灰度

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)

说明：  基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)