这是用verilog硬件描述语言编的5分频代码

用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

基于VHDL的TPC译码器的设计，简述了tpc译码的算法步骤，tpc硬件实现的模块和部分vhdl程序(TPC decoder VHDL-based design, outlines the decoding algorithm steps tpc, tpc hardware modules and some vhdl program)

least mean square algo implemented on verilog

小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)

可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf

LTE上行链路使用的DFT-S-OFDM系统的仿真，其中包括QPSK星座映射、串并转换、N点DFT、子载波映射等。(LTE uplink using the DFT-S-OFDM system simulation, including QPSK constellation mapping, string and conversion, N-point DFT, subcarrier mapping, etc..)

基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏！（可以使用RS2键盘进行控制）(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))

UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder

VHDL book for reference

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！