Vhdl实现计算exp功能 在apex20k上经过验证

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

rsc递归卷积编码器是turbo码的分量编码器，递归相对于普通的卷积码多了一个反馈，拥有更好地重量谱分布和更加的误码率特性，且码率越高，信噪比越低其优势越明显。利用D触发器组成的rsc生成器，逻辑思维简单，里面包含有测试波形以及测试的结果

VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier

说明：  VHDL资料 很不错的！！！！！！！！！！！(VHDL )

VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)

三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)

分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.

Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)

文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)