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clock
本程序实现数字钟系统,有整点报时功能,可显示切换年月日,定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分:1
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f500
verilog coding for butterworth filter with cut off
frequency with 500hz
- 2014-02-19 15:37:09下载
- 积分:1
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1024点FFT快速傅立叶变换,包含说明文档和VHDL源代码,16位输入/输出,带DMA功能,xilinx的ip...
1024点FFT快速傅立叶变换,包含说明文档和VHDL源代码,16位输入/输出,带DMA功能,xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input/output, with DMA function, the ip xilinx
- 2022-10-07 06:50:03下载
- 积分:1
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xge_mac_latest.tar
用Verilog编写的以太网控制器,可以使用,里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)
- 2015-12-21 17:12:51下载
- 积分:1
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detection of the following sequence ‘10110110’in VHDL
detection of the following sequence ‘10110110’in VHDL
- 2023-04-17 19:05:03下载
- 积分:1
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fft
FPGA实现FFT算法的源代码及工程文件,此工程为ISE工程项目。有详细的说明,可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分:1
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两个例子提醒我们如果我们要使用锁存器则不需要任何操作,如果我们想避免锁存器的话,我们要让这个元器件的每一个可能条件赋予一个值...
两个例子提醒我们如果我们要使用锁存器则不需要任何操作,如果我们想避免锁存器的话,我们要让这个元器件的每一个可能条件赋予一个值-signal or variable "" may not be assigned a new value in every possible path through the Process Statement
- 2022-05-22 18:34:33下载
- 积分:1
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Harris-algorithm-based-on-FPGA
在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时,对一些较为复杂或者重复性工作模块多的情况下,算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益,还可以对程序有较详细的估计,在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module,it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)
- 2013-02-28 15:41:39下载
- 积分:1
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data_swith
verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分:1
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四VHDL模块的家庭,已经过测试,在ISE8.1通过
四位全家器的VHDL语言模块,已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through
- 2022-03-21 16:25:17下载
- 积分:1