在 FPGA 中实现 SPI 接口

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

iic 总线 verilog 源代码 标准i2c总线， 有sda scl 时钟，频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)

CAN驱动器MCP2515驱动，verilog编写，实测可用(CAN driver MCP2515 driver, Verilog written, measured available)

8051的Verilog-Verilog OF 8051

潘松编写的EDA书籍！学习FPGA的好帮手！-Pinson prepared by the EDA books! Learning FPGA a good helper!

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

IIC控制器 for Sopc Builder-IIC controller for Sopc Builder

说明：  学习fpga的工具signaltap软件使用说明书，好工具(Learn the instruction manual of signaltap software, a good tool)

标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作(Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA )