FFT的VHDL代码

实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.

program in hdl that this open mind in digital resources

关于一个串行数据输入 根据时序将数据分两路输出的程序 (on a serial data input timing will be based on output data using two procedures)

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)

完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)

verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms

说明：  基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)

ALTERA　NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface

数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)

quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE