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FIR滤波器的基本Verilog代码实现
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2022-03-31 20:42:11下载
- 积分:1
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DE2_NIOS_HOST_MOUSE_VGA
基于nios的vga显示实验,自制的ip核。可以按照自己的需求改写ip(Nios to vga display ip nuclear experiments, homemade. Can be rewritten in accordance with their own needs ip)
- 2021-04-11 11:58:58下载
- 积分:1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分:1
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- 2022-03-20 01:15:24下载
- 积分:1
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zzlB
QUARTUSII 9.0 下的三级流水线中值滤波工程,vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
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- 2011-12-21 16:17:41下载
- 积分:1
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DTMB
能够完美产生数字地面电视(DTMB)的信源的程序。帧头模式为模式一。信道可选择,信号加入频偏,延时,后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分:1
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a
说明: 用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分:1
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ATSC发送端部分,ATSC标准特有的TCM编码,共6个文件,包含tb文件,已通过仿真,没有问题,verilog代码...
ATSC发送端部分,ATSC标准特有的TCM编码,共6个文件,包含tb文件,已通过仿真,没有问题,verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
- 2022-03-11 13:26:28下载
- 积分:1
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一个基于fpga的源程序,对于初始接住的人来说很有帮助
一个基于fpga的源程序,对于初始接住的人来说很有帮助-FPGA-based source for the initial very helpful for those who catch
- 2023-01-04 08:05:03下载
- 积分:1
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1