异步串行接口电路及数据传输模块设计

MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test

FPGA入门点亮一个LED灯，作为FPGA入门级程序(FPGA is)

说明：  用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能(for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on)

在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)

运用Quartus在LCM中显示静态宫殿图形-Use Quartus in LCM display static graphics palace

串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.

说明：  ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)