This procedure for the Verilog control ADC all procedures can be applied to test

说明：  学习vhdl硬件描述语言的一些例子的原代码(VHDL hardware description language to learn some examples of the original code)

检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify

lap trinh FSM may trang thai

基于CS的一维距离像（HRRP）及FFT成像对比(CS-based HRRP and FFT HRRP)

Convolotional Decoding Based on Viterbi Algorithm

ODBC编程实例，使用ODBC对基于开关量数据采集卡的通信接口设计与实现。(ODBC programming examples, using ODBC for data acquisition card based digital communications interface design and implementation.)

说明：  能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

Bucknell Verilog Manual

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners