This procedure for the Verilog control ADC all procedures can be applied to test

在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory

用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

基于FPGA的抢答器程序，VHDL 语言描述。(FPGA)

本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming

在vhdl开发环境下，关于协议PS2 verilog 源码-In VHDL development environment, with regard to the agreement PS2 verilog source code

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)

this code to input 8 different data and make them out sequentialy

I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.