VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)

说明：  CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。 本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

说明：  掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

Altera DE1平台的数字密码锁设计，可以驱动VGA显示(Altera DE1 platform digital password lock design, can drive VGA display)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

我是复旦的研究生。这是用VHDL写的ALU，仿真通过，压缩包里包括了每个源代码，而且都有相应的testbench，你直接加入你的工程当中就可以进行验证。设计时。我使用Modelsim环境来编写的。

高频卡读写原理及技术编程应用--卡的读取，写入。(High-frequency card reader technology)