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The design of digital self
数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
- 2022-08-10 00:17:42下载
- 积分:1
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QPSK_1
QPSK调制,QPSK仿真误码率,QPSK理论误码率 , QPSK仿真误比特率 , QPSK理论误比特率 (QPSK modulation, the signal-to-noise ratio)
- 2020-12-06 19:29:22下载
- 积分:1
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NIOS II IDE 编程, uart_txd测试程序,仅供参考。
NIOS II IDE 编程, uart_txd测试程序,仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.
- 2022-11-30 03:45:03下载
- 积分:1
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VHDL ip core的设计,软核的设计方法
VHDL ip core的设计,软核的设计方法-VHDL core of the design, soft-core design
- 2022-06-01 06:05:02下载
- 积分:1
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bubblesort
根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果,含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)
- 2021-05-08 13:28:35下载
- 积分:1
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dct01
Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)
- 2011-01-17 02:40:41下载
- 积分:1
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tlc549adc
FPGA AD数据采集模块,实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)
- 2021-04-14 21:08:55下载
- 积分:1
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Data Encryption Standard or DES
加密已经成为我们生活的一部分,我们
- 2022-04-28 04:42:22下载
- 积分:1
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LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分:1
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cpld/fpga common adder Verilog design procedures
cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
- 2022-08-19 10:20:20下载
- 积分:1