比较适合初学学者，而且比较基础。描述的不全面，先看看吧...

URAT VHDL程序与仿真 URAT the VHDL program and Simulation (URAT the VHDL program and Simulation )

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

AES 128 bit with various device interface on FPGA

学习xilinxVHDL语言的一本好书，为官方资料，可方便读者熟悉xilinx的代码风格(A good VHDL,it s fittable for the reader to be familiar with the style of xilinx)

---------------------------------------------------------------------------------- -- Company:       VISENGI S.L. (www.visengi.com) - URJC FRAV Group (www.frav.es) -- Engineer:      Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com) -- -- Create Date:    12:39:50 06-Oct-2008 -- Pr

ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)

用NIOSII生成的VGA显示程序,可以在显示器上显示通讯内容

ARM+FPGA JTAG(二合一)原理图与PCB(ARM+ FPGA JTAG (combined) schematic and PCB )

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

its a Fifo BASED design i also Interface DAC2904