vhdl应用汇编所写的关于电梯的详细程序

说明：  学习使用quartus modelsim(learn to uee quartus modelsim)

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such as VHDL and Verilog (The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog)

说明：  fft代码,采用蝶形算法,包括C,matlab和verilog代码(fft code, using butterfly algorithm, including C, matlab and Verilog code)

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)

说明：  FSK VHDL FSK调制与解调VHDL程序及仿真(FSK VHDL )

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures

FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

a big number class and a calculator using the class

资源描述VGA视频图形阵列（VGA）接口是一三排15针de-15连接器。15针VGA接口是许多视频卡，发现电脑显示器，以及一些高清晰度电视机。在笔记本电脑或其他小型设备，迷你VGA端口有时用于全尺寸的VGA接口的地方。