vhdl应用汇编所写的关于电梯的详细程序

VLSI Implementation IEEE Papers 2010 to 2014

基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。(8B10B encoder)

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

改变学习板上的2个电位器对应的2段模拟输入，实现模拟输入，学员观察数码管的数字变化情况,通过改D[4]的值，实现模拟输出.(Changing the learning board two potentiometers corresponding paragraph 2 analog inputs, analog inputs, digital tube digital trainees observe the changes, by changing D [4] value for analog output.)

FPGA to design in ECU, very help for engineer

this is the vhdl code for the arithmetic logic unit.enjoy!

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

double edfe trigger d latch

本例源代码文件由用户按照书中的操作步骤自己生成，“Example-2-1Project_Navigator_Demo源代码”目录下为源代码的参考文件。“Example-2-1Project_Navigator_Democounter”目录下为完整的工程，包括源代码文件、综合与实现的结果文件、ISE工程文件等，可以使用ISE工程管理器打开工程，供读者参考(In this case the source code files by the user in accordance with the steps the book itself is generated, "Example-2-1 Project_Navigator_Demo source" directory as the source code reference document. "Example-2-1 Project_Navigator_Demo counter" directory for a complete project, including source code files, integrated with the realization of the outcome document, ISE project file, etc. You can use ISE Project Manager, open the project for the reader is referred to)