HDL编程风格，很有用,希望对大家有所帮助。

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code

本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  参照can芯片 saj1000控制器结构，写的can控制器(According to the structure of can chip saj1000 controller, the CAN controller is written)

FPGA——IP_RAM实验： 创建IPRAM核，单端口，10位地址线（256字节），8位数据线（每字节8byte），读写使能 input [9:0] address; input clock; input [7:0] data; input wren; //置1则写入 output [7:0] q; LNXmode：控制LEDC显示 1：mode1，从k1~k3输入data的低4位，ledb计时，从0~f，计时跳变沿读取k1~k3的值，存入RAM 8个数之后，从RAM输出数据，用leda显示，同样每秒变化一次(The experiment of FPGA-IP_RAM: Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)

自动售货机程序(Vending machine procedures)

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging

一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)

实现两路数字信号的鉴相功能，最后通过静态LED显示出来，该程序通过硬件的测试-Realize two-way digital signal phase function, and finally through a static LED display, the program through the hardware test