This an interpolating by 2 half

用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted

本文分析了当前国内外出租车计费系统的基本组成和工作原理及主要的两种设计方式:基于单片机的设计方式和基于FPGA的设计方式；并对这两种实现方式的优点和缺点进行分析，比较后确定本系统的方案：基于FPGA的出租车计费系统的设计。(This paper analyzes the current taxi charging system at home and abroad, working principle and basic components of two major design approach: the design methods based on single chip FPGA-based design approach and the two implementations to analyze the strengths and weaknesses, After comparing the program to determine the system: FPGA-based taxi billing system.)

fpga高手设计实战真经100则,最新的FPGA英文书籍，值得参考学习(100 Power Tips for FPGA Designers，The new FPGA English books, worth learning)

这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

用于单片机的adc采集实验，经过降噪处理，结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture

在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)

Verilog OTP ROM source code

16卫浮点FFT算法的VHDL实现，有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.