拔河电路的设计

Implementation of Serial Infrared decoder for low-speed IrDA communications.

open cores 提供的i2c控制IP核 可直接在FPGA上使用。并带有相关的测试程序(endorsed by the i2c controller IP provided by the open cores on the FPGA. With the relevant test procedures)

电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach

基于FPGA的VERILOG语言的DS18B20温度检测程序，代码自测可用(FPGA based VERILOG language DS18B20 temperature detection program, code self test available)

ＦＰＧＡ与ＳＤＲＡＭ　的　ＶＨＤＬ　接口设计(ｔｈｅ　interface of FPGA and SDRAM)

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

IEEE Standard for Verilog 2005

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)