这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着...

给予QPSK调制的OFDM例程，简单明了的表述了OFDM的通信原理(Given OFDM QPSK modulation routine, simple expressions of OFDM communication theory)

SPI经典ip核 可以直接用于工程的开发和利用-err

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

数字频率计(试验报告)适合初学者参考-Digtal Frequency Test(experiment report) suit Raw recruit reference

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING

Spartan 3e - Active Power Meter-Spartan 3e- Active Power Meter

FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM