这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着...

一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source

：采用FPGA来实现一个基于OFDM技术的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制器包括：信道编码（Reed-Solomon编码），交织，星座映射，FFT和插入循环前缀等模块。我另外制作了相应的解调器，可以实现上述功能的逆变换。(: Using FPGA to implement a technology-based OFDM communication systems in base-band data processing part of the modem. One part of the modulator launch include: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and cyclic prefix insertion modules. I also produced a corresponding demodulator can achieve the above-mentioned inverse transform function.)

用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)

USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of

D触发器的基本功能的理解及应用，特别是记忆传输功能使用WAIT语句编写地理解-D flip-flop understanding of the basic functions and applications, in particular the memory transfer function using the WAIT statement is prepared to understand

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

IIC slave controller source code

单相混合有源电力滤波器的设计与控制，在matlab中的仿真模型，功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)

最近交互式电源技术，软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)