-
power_control
四轴动力模块,用一个顶模块控制,输入有:油门(20档);指令;水平仪控制指令,4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)
- 2013-12-26 20:57:03下载
- 积分:1
-
2FSK
基于FPGA的2FSK调制解调,里面有详细的工程说明,对于学习ISE软件和通信原理的知识很有帮助(FPGA based 2FSK modulation and demodulation, which contains detailed engineering instructions, for learning ISE software and communication principles of knowledge is very helpful.)
- 2018-06-30 17:49:20下载
- 积分:1
-
是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间...
是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 -Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware
- 2022-01-26 02:12:56下载
- 积分:1
-
verilog实现自动售货机
能实现输入0.5 1 5块钱的累加,然后对应购买的商品价格进行比较,显示找的钱数或错误灯(MY English is very good)
- 2019-01-09 13:35:02下载
- 积分:1
-
8051的vhdl源代码,主要针对初学者
8051的vhdl源代码,主要针对初学者-8051 VHDL source code, mainly for beginners
- 2022-02-05 02:00:30下载
- 积分:1
-
Simulate
FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)
- 2021-04-14 21:08:55下载
- 积分:1
-
Camera-Interface-Overview
主要讲述了数码相机MIPI接口协议说明,工作模式及信号传输原理等(Camera Interface Overview)
- 2014-01-20 22:19:32下载
- 积分:1
-
用VerilogHDL编写的,一个占空比为50%的6分频电路
用VerilogHDL编写的,一个占空比为50%的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
- 2023-06-23 12:25:03下载
- 积分:1
-
check_net_test
用来检查FPGA通过PHY发送数据时是否有掉帧的现象(FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of)
- 2011-11-18 10:28:02下载
- 积分:1
-
用VHDL语言来实现一个电子时钟,可以调时间。小时,分,秒。可以下载到实验箱来运行验证。...
用VHDL语言来实现一个电子时钟,可以调时间。小时,分,秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
- 2022-07-21 04:12:49下载
- 积分:1