Discrete cosine transform and inverse discrete cosine transform of the HDL code...

鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD

基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)

it is used to compile codec

使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,(the modulation of 16QAM based on FPGA)

采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作-Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly

sdram控制器的开发程序，还有文档，可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)

该资料为基于FPGA 的NAND flash控制器研究，语言为VHDL，代码已通过仿真验证

VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display

VHDL参考手册，从事FPGA的好帮手，FPGA学院的终身伴侣！-VHDL Reference Manual, in FPGA a good helper, FPGA college life companion!