基于FPGA五子棋显示verilog源代码

全部通过，是我的精心设计，完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting

学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.

在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。-In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

quick reference guide to verilog HDL

一个用VHDL编写的跑马灯程序和60进制计数器的程序，一个是自己设计的一个是老师要求，都在实验箱上验证成功，希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.

NN CONTROLLER FOR UPQC

it will count the bit

使用Matlab Gui实现的数字信号处理常用算法，包括卷积，FFT，FIRIIR数字滤波器设计，最佳滤波器，自适应滤波，卡尔曼滤波等

电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text Foreign electronic and communication textbooks)