FPGA控制的SRAM接口不分的设计

11阶滤波器的verilog编程语言，可很好的实现滤波功能。-11-order filter verilog programming language, can achieve very good filtering.

说明：  快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)

自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,

The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.

数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能(Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function)

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)

测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)

基于Verilog语言编写的LCD1602显示的日历程序，类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)

任意数据发生器的源代码-arbitrary data source code generator

说明：  华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码，使初学者能够迅速熟悉基本的HDL 建模；同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)