verilog写的数字频率计的控制模块,对程序进行控制

design through verilog hdl

例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)

PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)

lacp代码，可以参照学习Lacp协议的相关状态机等知识(LACP code, can refer to the relevant state machine learning knowledge of Lacp protocol)

vhdl的源文件调试 ！！！！！！！！ flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video

it is a matrix library. it is needed for fir fier.

一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)

说明：  经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。(fpga exampe)

GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device