通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。

Verilog编程语言经典手册Classic Manual Verilog programming language(Verilog programming language classic manual Classic Manual Verilog programming language)

FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface

在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。(Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by. )

基于FPGA实现的神经网络算法ANN。针对手势识别，不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks Implemented in FPGA)

说明：  DDS VHDL include everything of dds AD9914

这是一个vhdl代码的进位选择加法器及其工作100%。

vhdl programming from beginner level

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural