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Ver_I2C_eeprom
用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM,代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)
- 2013-04-10 16:14:03下载
- 积分:1
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A4_Led3
说明: led学习控制l44444444444444(led verilog led ccccccc)
- 2019-05-06 09:38:14下载
- 积分:1
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MP3播放器与VS1003 ATmega8的和SD卡
这是一个版本的mp3播放器的迷你尺寸,你可以把它与AVR编程非常easy.it在这个项目这么简单,你使用的fat通过MMC的SPI总线,该总线使主从位置发送数据,然后用此主从,你可以从VS1003发送数据到你的ATmega8然后有一个非常简单的项目。
- 2022-04-29 02:58:41下载
- 积分:1
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Verilog
说明: Verilog简易教程,或者说是讲义,清晰易懂,适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)
- 2010-04-08 16:51:54下载
- 积分:1
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It is a fir to implement in a FPGA. It s not desenvolved for me it is a good wor...
It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
- 2022-03-29 20:48:40下载
- 积分:1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分:1
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高效的同步有限状态机的设计,本代码详细的说明了如何设计高效和规范的fsm设计...
高效的同步有限状态机的设计,本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
- 2023-07-18 00:50:02下载
- 积分:1
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led5604
说明: 5604FPGA驱动,能显示数字(5604里面为4个595)(5604 FPGA driver, able to display digital (5604 contains 4 595))
- 2020-06-19 18:00:01下载
- 积分:1
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vhdl经典源代码――键盘接口设计,入门者必须掌握
vhdl经典源代码――键盘接口设计,入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master
- 2022-11-20 22:55:03下载
- 积分:1
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ALU_4bit
4位ALU,有两个4位输入,4位输出实现逻辑运算和算术运算,逻辑与或非,加1,减1等等功能(4 ALU, logical and arithmetic operations)
- 2012-11-18 18:04:59下载
- 积分:1