AV视频信号输入后，存入SDRAM中然后在PC上面进行显示的代码。...

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm

文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和 设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and Design of high resolution, high stability function of the signal )

this the for a equiripple filter-this is the for a equiripple filter

说明：  I2C MASTER DESIGNED by Verilog

在zedboard上运行的神经网络架构，方便移植。(Run lenet-5 on zedboard)

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.

验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)