AV视频信号输入后，存入SDRAM中然后在PC上面进行显示的代码。...

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend

直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。 采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。 此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。 本实验在设计的模块中，包含以下功能： （1）通过 freq 信号输入需要的频率的值； （2）通过 wave_sel 信号选择所需的波形； （3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)

电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

ASIC design and synthesis

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)

半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)

说明：  用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)

ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.