VGA count, PSW2 inverse control is counting? Reduced count, pop

micron公司提供的控制器，很具有参考性质，用flash的童鞋可以下载参考，含有ECC功能

本文提出了一种新颖的可逆乘法器。可逆逻辑可以发挥重要作用

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera

说明：  反应力测试 利用图片的变换根据用户点击的反应时间判断(Reaction force measurement using the picture of the transformation reaction time based on user clicks judgment)

基于FPGA的出租车计价器，欢迎大死同学多多交流(FPGA-based Taximeter, welcomes the dead students more exchanges)

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)

VHDL学习总结，简要概括了VHDL，非常适合做学习的总结-VHDL study conclusion, a brief summary of VHDL, very suitable for learning to do a summary of

关于FFT实现的Verilog代码，(FFT realize on the Verilog code,)