VGA count, PSW2 inverse control is counting? Reduced count, pop

verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)

基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)

A Dec example written in VHDL.

verilog_ad0809 cpld control

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.

此为数字逻辑书上的答案，应该很多同学都需要吧，关于数字逻辑(This is the answer books, digital logic, it should be a lot of students need it, on the digital logic)

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

an example HDL-Core with any basic gates.

Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)