fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)

包含DCT变换，RGB2YCBCR,JPEG等多个verilog代码及工程(Contains DCT transform, RGB2YCBCR, JPEG and many other verilog code and project)

采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化(VHDL hardware description language using the dual-caliber RAM block memory initialization)

adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)

一个7段的显示器，及按一定顺序循环得到的结果，可重复使用(A 7-segment display, and by a certain sequence and cycle the results obtained can be reused)

8086微机原理实验：8251串行接口、8253计数器、数码管、跑马灯。汇编语言。(8086 microcomputer principle experiment: 8251 serial interface, the 8253 counter, digital tube, Marquee. Assembly language.)

数字钟，简单的数电应用，电子表源程序，常用也使用-watch

在 VHDL 中实现的游戏 实施LFSR创建与随机游戏板 随机颜色。使用VGA控制器和块内存 我们显示游戏板，并写入它取决于某些规则。用户 可以控制如何密游戏板填充，则显示什么颜色， 而如何快速模拟。

nrf24l01发送代码，verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)

Ethernet Media Access Controller