fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

FPGA应用举例，非常适合初学者，高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo

24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.

16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!

基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design

XAPP585 serdes_1_to_7 and serdes_7_to_1 data

16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source

此程序描述了数字电路中与门的逻辑功能。所采取的硬件描述语言为VHDL。程序结构采用了dataflow的写法。请大家仔细阅读。本程序已通过了Altera quartus的验证。确保准确无误。

Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions

OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders