fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

说明：  FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)

cordic的verilog程序 用ＦＰＧＡ实现-CORDIC FPGA using the Verilog procedures realize

vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of

刚写的一个44键盘程序，调了好多天才调出来，给大家提供参考。-Just write a 44 keyboard program, tune out of tune a lot of talent to give you a reference.

cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design

本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

this file is vhdl code of alu