fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

可直接用于zedboard上的串口通信，利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

single cycle mips design by verilog.

这篇是利用VHDL语言控制LCD1602芯片来显示时钟的简单代码。LCD1602顾名思义是一种02*16，即为两行十六列的液晶显示屏，液晶两行，每行可以显示16个字符，但是CGRAM及CGROM里面一共有160个字符，包括阿拉伯数字，英文字母大小写，常用符号及日文。每个字符对应于一个ASCII码值，在液晶显示屏上显示对应的字符时候，只需要将对应的ASCII码写到DDRAM中就好。

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)