fft in dspbuilder under VHDL source code and test incentives document matl ab mo...

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

DE2-115开发板TV摄像头成像程序，源码亲测可用，可加入边缘算法成像，实时显示轮廓，速度流畅(The DE2-115 development board TV camera imaging procedures, the pro-test in the source can be added to the edge algorithms imaging, real-time display contours, fast-paced)

2维4节点的UEL单元，嵌入UMAT，采用j2 mises屈服准则(2d4nodes uel elements, with umat codes, and j2 mises flow rule)

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

此源码为线性相位滤波的vhdl源码与设计心的体会，理论分分析与工程实践总结相结合，有非常大的参考价值 可直接使用。 (The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)

VHDL数字电路设计的电子书，很好的学习材料-VHDL digital circuit design of e-books, very good learning materials

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.

How to Connecting Xilinx FPGAs to the Philips

1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)