一个快速和简单的斯巴达教程3

利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count )

max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)

基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)

PWM for control of motors

This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps

vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.

Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm

自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)

大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51

FPGA的SRAM存储器的控制程序，包括时序测试-FPGA