一个快速和简单的斯巴达教程3

按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)

ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99

Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license

静态RAM是由MOS管组成的触发器电路，每个触发器可以存放1位信息。只要不掉电，所储存的信息就不会丢失。因此，静态RAM工作稳定，不要外加刷新新电路，使用方便。但一般SRAM的每一个触发器是由6个晶体管组成，SRAM芯片的集成度不会太高，目前较常用的有6116（2K×8位），6264（8K×8位）和62256（32K×8位）。6264RAM有8192个存储单元，每个单元为8位字长。-Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not brown-out, the stored information will not be lost. Therefore, the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of six transistors, SRAM chip integration will not be too high, there are currently more commonly used 6116 (2K × 8 bit), 6264 (8K × 8 bit) and 62256 (32K × 8 bits). 6264RAM have 8192 storage units, each for 8-bit word length.

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)

altera 公司的15IP源码 亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER

UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)

32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only