对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流...

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

基于DDS和SOPC的谐波信号发射器，拥有可调节的频率，阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)

ad9957的资料，内含有命令字生成器，适合使用该芯片的开发人员(ad9957 data, contains the command word generator for developers using the chip)

固定的 128 点复杂 FFT 或 64/8/16 点

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)

I2C配置tvp5150用VHDL写的 -I2C configuration tvp5150 written using VHDL

VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)