对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流...

基于FPGA的快速傅立叶变换实现，适合fpga工程技术人员参考设计-FPGA-based Fast Fourier Transform for fpga reference design engineers

基于Verilog的数码管模拟扫描程序，分为两种显示方式，一种是数码管逐个显示，另一个是所有数码管一起显示。-Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.

ISE Design Suite Software Manuals and Help - PDF Collection,ISE 软件手册以及帮助。(ISE Design Suite Software Manuals and Help- PDF Collection, ISE software manuals as well as help.)

FPGA生成伪随机数,希望对加密的童鞋有用(FPGA generates pseudo-random numbers, we want to be useful)

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)

该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。(This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)