Common examples of VHDL, suitable for beginners, there are examples of commonly...

使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)

Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until

可在FPGA上运行的8051 IP coore，是学习FPGA及SPOC的好资料。 (8051 IP coore, can be run on the FPGA is good information to learn FPGA and SPOC.)

用Bresenham算法在FPGA上实现小数分频器，verilog编写，计算机图形法-Bresenham algorithm used in the FPGA to achieve a small number of crossovers, verilog preparation, computer graphics method

The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.

这个是vhdl的彩灯实例程序，里面涵盖了48种的彩灯变化，通过了maxplus的验证，并且在机上实验通过-this is the Lantern example VHDL procedures inside covers 48 species of Carnival changes adopted maxplus certification, and the plane through experiments

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)

一个交通灯设计,简单的实现，没有添加其他的显示管(Traffic Light System)

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Vhdl design z80 for altera users