Verilog HDL language proficiency of a good cpu code

清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。(Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.)

这是“VHDL设计”讲稿，希望对初学者有用，-"VHDL design" script, useful for beginners, thank you! !

tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master

這裡提供Auto Gain Control 的詳細代碼與功能介紹(Here are details of the code and the Auto Gain Control Functions)

tms320c6747的测试程序 。用于dsp各个模块的测试，很好的例子(dsp tms320c6747)

说明：  在FPGA板卡上面，通过单个按键实现串口的发送功能，带仿真需要自行修改一下工程配置(On the FPGA board, the sending function of the serial port is realized by a single key, and the engineering configuration needs to be modified by the simulation)

VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA

基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生(puls wide modulator based on delayline)

自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)