1553B的编解码程序是有用的给大家分享分享

XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创-XC95144 stepper motor drive source, using verilog vhdl development, personal originality

数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。-digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions .

基于VHDL语言开发的mcu与外部器件的接口程序，解决了高速mcu与低速外部器件的接口问题。-based on VHDL development mcu with external device interface, mcu solve the high-speed and low-speed external device interface.

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

spansion file system包括FTL功能, 支持NAND, NOR, SPI flash.(spansion file system including FTL module, support NAND, NOR, SPI flash.)

2位并行加法器初学者必看初步了解FPGA-two count

在FPGA内使用PID算法反馈控制小车速度和方向，四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)

在硬件上实现,可以实现一般电子表的功能。比如说计时，显示日期，秒表等功能。还可以显示星期数，可以正常的区分闰年等。并且仿真文件也在其中，反正了其时序变化情况。比较详细。必要出有注释。

This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1. PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.

有单极倍频功能的matlab spwm逆变器(Unipolar multiplication function the the matlab spwm of inverter)