8051 verilog achieve, enclosing testbench, c language debugging procedures

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through

How to Connecting Xilinx FPGAs to the Philips

说明：  串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)

用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)

一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)

VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit

利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl

Digital Design and Modeling with VHDL and Synthesis

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )