8051 verilog achieve, enclosing testbench, c language debugging procedures

说明：  ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)

它包含与试验台硬件描述语言(VHDL)一半加法器试验台意味着项目制造商宣布他要什么时候能给一个术语 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)

基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using

FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD

用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)

Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)

tlm基本框架，生产消费模型例子 tlm基本框架，生产消费模型例子 tlm基本框架，生产消费模型例子(tlm basic framework, examples of production and consumption model)

本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。