vhdl学习程序

ecc椭圆算法RTL,verilog源代码经过验证，用于FPGA或者ASIC(ECC elliptic curve encryption algorithm for Verilog implementation)

基于MAX2运用Quartus实现串口通信-MAX2-based use of Quartus Serial Communication

VHDL operators basics

Use verilog language design DIGITAL-PID source

有自己制作的下载器原理图，包含了stlinkv2,XDS100V3,USBBLASTER.原理图和封装，一款多功能下载器。(Have their own production downloader schematic diagram, contains stlinkv2, XDS100V3, USBBLASTER. Schematic diagram and encapsulation, a multi-function downloader.)

用VHDL语言实现TDMA编码,简单，明了。看标注就可以看懂-use vhdl langhanTDMA

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

说明：  BUS documentation and map reffereces

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code

lgpl RS编解码 5-6 Reed-Solomon Codes-LGPL RS codec 5-6 Reed-Solomon Codes