Viterberi 解码器

Convert Roman numerals to integers

说明：  这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)

关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures

基于FPGA的1553B总线编码解码器的设计-1553B Bus FPGA-based codec design

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

新版 小米抢购器 -源码 已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source Have test, the code is useful, has robbed several millet 3, hope useful for everyone)

程序设置了fpga 的 5x5点阵驱动程序，代码相对比较简洁，这个程序可以作为fpga输出控制，驱动稳压芯片工作，进而点灯

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)