Viterberi 解码器

NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.

Verilog 我认为写的非常好的细节书(Verilog In my opinion written details of the book)

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

I2C EEPROM 存取源碼, 通用ATMEL(I2C EEPROM read/write)

本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)

说明：  良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

说明：  802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)