Three

巴克码装到信息内同时将巴克码识别出来，实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

96x96 Digital MUX/DEMUX via SPI

Introduction to learn laboratry with altera quartus II 9.1

VGA字符显示VHDL程序 可以直接用于工程的设计与开发-VGA display characters can be directly used for VHDL design and development

简易双口ram，使用两个ram ip core，一个写的同时另一个读，并且包含按键使能和数码管以及流水灯显示(Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show)

ATSHA204_S加密芯片资料，学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)

DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit(DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit)

采用骏龙科技这个13.1新版本破解器.对于已经用了老版本破解器的网友，请把bin和bin64下的sys_cpt.dll删除，然后把sys_cpt.dll.bak名字改成sys_cpt.dll，也就是先恢复正版，然后用这个破解器破解。注意老的license文件也要删除，改用这个新版本破解器附带的license(Cytech Technology 13.1 using the new version of this cracker. Has been used for the old version cracker users, please sys_cpt.dll bin and bin64 under Delete, and then changed the name of the sys_cpt.dll.bak sys_cpt.dll, which is first restore genuine, then use this cracker to crack. Note that the old license file should be deleted in favor of this new version of the license that came with crack)

这是一个数字逻辑课程的电子表的实现，利用VHDL语言实现，初学者可以完全掌握，很有帮助。