FPGA

本程序用于实现OFDM信道估计的LS算法的硬件仿真，基于FPGA开发的VHDL编写，给出了各模块的仿真波形图，供大家交流参考。

可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)

QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information

TI公司的DAC5578驱动程序，经测试过的，CSDN资源分享(DAC5578 Driver of TI Company Tested and CSDN Resource Sharing)

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~

电路酒窖杂志的vhdl示例。vga控制器、视频发生器等PS2鼠标vhdl

说明：  Verilog语法教程，适合初学者，详细(Verilog instruction book)