FPGA

基于DE2开发板的VGA显示模块，仅供大家参考(DE2 development board based on the VGA display module, for your reference)

在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。(In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.)

数字逻辑课程设计，用vhdl实现红外线传输系统的课程设计，下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

温度液晶显示演示程序 LCD数据线：P0口 LCD控制线：RS P20 RW P21 E P22 BUSY P07 18B20端口DQ ：P27 (Temperature of liquid crystal display demo Data line: P0 LCD LCD RS P20 RW P21 control line: E P22 BUSY P07 18B20 DQ : P27 port )

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)

Priority encoder in VHDL.