FPGA

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

说明：  16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

说明：  ip core of the transceiver gtx

基于FPGA的数字电压表 两种方案 一种VHDL一种Verilog(Digital voltmeter based on FPGA)

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

Once the FPGA is located, the rest of the mapping data for the other components can be determined dynamically its section mapping registers.

用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.