用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2...

poor scope is a vhdl implimentation pic micro controller

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation

用Verilog实现的交通信号灯控制，主干道和支路通行的时间不相等(Using Verilog implementation of traffic signal control, the trunk road and the slip is not the same passage of time)

实现一个简单的电子钟，其时间（时，分，秒）可以设置和更改，设置和更改的同时不会影响其他显示的变化（相互独立）。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

用FPGA单片机软核实现键盘扫描，键盘为4X4矩阵键盘，输入相应键值，用数码管显示-keyboard

ATSHA204_S加密芯片资料，学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)

基于Verilog的PCI总线接口的设计及应用-Verilog-based PCI-bus interface design and application.

非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)

FPGA based design and Implementation of Advanced Encryption Standard